The present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to a semiconductor structure including at least one field effect transistor (FET) having a stressed channel and a metastable embedded, strained epitaxial semiconductor material located at the footprint of the at least one FET.
One trend in modern integrated circuit manufacture is to produce semiconductor devices, such as FETs, which are as small as possible. In a typical FET, a source and a drain are formed in an active region of a semiconductor substrate by implanting n-type or p-type impurities in the semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
In order to maintain FET device performance with continued scaling, it has been necessary to use mobility enhancement techniques. One of the most effective and widely used mobility enhancement techniques is referred to as “strained Si”. In such a mobility enhancement technique, an embedded SiGe layer (also referred to as eSiGe) is grown with selective epitaxy in the source/drain regions of the device.
Since the introduction of eSiGe, various process and device integration techniques have been introduced to increase the channel strain of the device. The most obvious of these enhancements is to increase the Ge content of the epitaxially grown SiGe layer. Although an eSiGe layer having an increased Ge content can provide enhanced mobility for CMOS devices, increasing the Ge content of an epitaxial grown SiGe layer is filled with difficulty in that any subsequently performed implant or anneal may result in defect formation and strain relaxation within the epitaxially grown SiGe layer.